What is SPI?
- SPI is serial, four wire, single master, full duplex interface.
- SPI was invented by Motorola and was designed to support short distance (on board) communication.
- SPI is widely used for interfacing FLASH, EEPROM, ADC, DAC, sensors and other devices to microcontroller. It is also good option for communication between two microprocessor.
How fast SPI can transfer data?
Generally, SPI can transfer data up to 10Mbps. However it depends on hardware design and device specification. Device datasheet should contain this information.
Who is master and slave in SPI communication?
Master is SPI device which initiates and terminates data transfer and responsible for generating clock signal.
Slave is device enabled/disabled by master using "slave-select"( or "chip select") signal and can never initiate data transfer on bus.
Master and slave devices both are capable of transmitting and receiving on SPI bus.
Note: SPI communication can have more than one slave but only single master.
Explain SPI master-slave topology.
How many slave devices can be connected to SPI bus?
Theoretically, there is no limit on how many devices can be connected to SPI bus.
Practically, how many devices can be connected depends on hardware design (bus capacitance, fan out) and application need (distance, speed etc.)
Explain SPI data transfer sequence assume single slave.
- Master generates clock
- Master pulls slave select line to low
- For each clock cycle master shift register sends one bit out on MOSI and slave samples it.
- For each clock cycle slave shift register sends one bit out on MISO and master samples it.
- Once all required bits are transferred master pulls slave select line to high and transfer ends.
Each data transfer is two way or full duplex in SPI, if master wants to read 8 bit data from slave, master will shift 8 bits on MOSI pin and slave will shift 8 bits on MISO pin. As shown in below image, master and slave connection can be visualized as virtual ring buffer.
What is CPOL and CPHA in SPI?
CPOL (Clock Polarity), defines idle state of clock line. Idle state could be low or high. CPOL determines that leading edge is rising edge or falling edge.
CPHA (Clock Phase), defines clock edge at which receiver can sample data and transmitter can send the data. This could be leading or trailing edge.
For SPI transfer, CPOL and CPHA both determines if data can be sampled by receiver at rising edge or falling edge. Based on this SPI defines four transfer modes as below.
What if slave device is not connected to SPI bus? How successful data transfer is ensured?
SPI doesn’t define any ACK mechanism like I2C, hence it is sole responsibility of application to implement logic to identify presence of slave device.
When there is only one way communication from master to slave, e.g. slave LCD device where master only writes the data and doesn’t read back anything from slave, in this case master will never know if slave device is connected or not.
However, if slave device is EEPROM in that case master can always read back after writing data and verify. If slave device EEPROM is not present, data verification will fail.
For an SPI communication, master needs to communicate with three slave devices having max clock support up to 2MHz, 4MHz and 6MHz respectively, What will be SPI clock frequency of master?
In SPI communication, always slowest slave device determines clock speed hence master will generate clock signal of 2MHz.
Out of all four SPI lines(MOSI, MISO, CLK, SS) which one needs to have tri-state output capability? Why?
MISO line needs to have tri-state output.
In SPI bus MISO lines of all slaves are connected together and for error free communication at a time only one slave device is required to drive this line.
To achieve this only currently selected slave will drive the MISO line and all other remaining slave will put their respective MISO line in high impedance state.
MISO line is not required to have tri-state output if only one slave is connected on bus or daisy chain slave configuration is used.