What is I2C?
- I2C is serial, two wire, multi master, half duplex bus protocol.
- I2C was invented by Philips in 1980's and was design to support short distance (on board) communication.
- I2C is widely used for interfacing EEPROM, LCD, RTC to microcontroller
How fast I2C can transfer data?
- Standard mode – up to 100 KHz
- Fast mode – up to 400 KHz
- High speed mode – up to 3.4 MHz
Who is master and slave in I2C communication?
Master is I2C device which initiates and terminates data transfer.
Slave is device addressed by master and can never initiate data transfer on I2C bus.
Master and slave devices both are capable of transmitting and receiving on I2C bus.
Explain single master-single slave, single master multiple slave, multi-master single slave, multi master-multi slave topology.
How many slave devices can be connected to I2C bus?
Theoretically, I2C has 7 bit and 10 bit slave addressing scheme and accordingly 128 and 1024 slave device addresses can be generated and connected on bus. Also 8 slave addresses are reserved for special purpose and future expansion.
Practically, how many devices can be connected depends on hardware design and application need (bus capacitance, distance, speed etc.)
Explain I2C data transfer sequence for transfer data of one byte assume single master and single slave.
What is START and STOP condition in I2C?
As it name suggests, START and STOP conditions are indication of I2C data transfer start and stop respectively. It can be generated by master only.
In case of multi master system, when bus is busy each master has to monitor/wait for stop condition on bus before attempting to start any new data transfer.
Why data (SDA) change is allowed only when clock (SCL) is low?
I2C device samples DATA on SDA line when SCL is high hence transmitter is allowed to change DATA only when SCL is low.
Also when SCL is high, change on SDA can be falsely interpreted as START or STOP condition by other masters.
What is repeat start condition? Why it is used?
When bus is busy, If START condition is generated by master instead of STOP condition, it is called repeat START. In multi-master system, repeat START is used by master to continue data transfer without releasing bus.
Why and how ACK mechanism is used in I2C?
ACK is indication from receiver to transmitter that address/data byte is received and receiver is ready for next reception hence transmitter can transmit next byte.
Every 9th clock pulse is used for ACK, transmitter releases SDA line during ACK clock pulse and receiver pulls SDA low during high state of ACK pulse.
What is NACK? When it can happen on bus?
If SDA remains high during ACK (9th) clock pulse, this bus condition is called NACK (not acknowledged).
This can happen in following condition.
- No slave device present on bus to ACK slave address and data.
- Receiver is busy processing high priority task and not ready to receive data.
- Receiver buffer is full and not ready to receive more data.
- Master receiver wants to indicate to transmitter that it doesn’t intend to read next data byte.
What is clock synchronization and bus arbitration?
In multi-master system, when bus is free it is possible that two or more masters starts transmission at the same time and starts controlling bus. However for error free data transfer it is required that at a time one master only gets full control of the bus and performs transfer and release bus for other masters once done. To achieve this clock synchronization and arbitration is used.
Clock synchronization is achieved by hardware using wired AND connection of SCL line. In this case SCL line low period is decided by master with longest low period and SCL line high period is decided by master with shortest high period.
Bus arbitration is also achieved by hardware using wired AND connection of SDA line. During arbitration when SCL is high, each master monitors/samples SDA line level and compares with level transmitted by self, if transmitted level by master on bus is high and low level is detected then master understands that it has lost bus arbitration and stops controlling SDA line. This way after transmission of first few bits only one master controls SDA line and completes transfer.
What is clock stretching? Why it is used? Is it mandatory to implement? What is it impact?
In I2C communication master is responsible for generating clock (SCL) and slave normally sends/receive data over SDA. At times, slave device may be slower than master and may not be able to send/receive data with clock speed generated by master. For example a slave ADC/EEPROM device is busy executing last Analog to Digital conversion/Memory write operation and not ready for transfer. In some cases slave device is other microprocessor and is busy executing ISR/high priority task and not ready for transfer.
To handle above situation, I2C communication has feature called clock stretching.
Clock stretching is an optional feature and many slave device may not include it. Once SCL line is released by master (after ACK for a byte) slave can pull SCL to low until it is ready for next transfer. Master is sent to forced wait state until slave is ready for transfer and this way slave device with slower speed can also easily communicate with high speed master.
Important point to note here is, with clock stretching overall bus data bandwidth is determined and reduced by slower slave device.
Why clock is bi-directional in I2C?
To realize multi-master and clock stretching functionality SCL is bi-directional in I2C.
Why open drain connection is used in I2C?
To realize clock synchronization, bus arbitration and clock stretching functionalities it is necessary that hardware is capable of allowing multiple devices to pull SCL/SDL lines high/low simultaneously and resultant line output state is wired AND of all inputs. This is achieved by open drain connection.
What is general call in I2C? Give one example of its usage.
General call address is special slave address (0x00) used to broadcast command from master to all connected slave device.
Master first sends general call address byte, if it is acknowledged by at least one connected slave device then master sends command byte.
If slave device doesn’t implement “general call” at all slave device can choose to ignore this. If slave device implements “general call” but doesn’t implement/recognize the command byte sent master then slave can only ACK the general call address and ignore the command byte.
Many times when master goes through unwanted reset (i.e. watch dog reset) to reset I2C BUS master may want to reset all slave devices also. General call can be used by master for this purpose. Below is an example.
Is there any way to cancel/abort ongoing communication?
START and STOP conditions detection logic is different from all other processing for data transfer. Hence when this conditions are generated any time during transfer I2C compatible device should abort ongoing communication.
Is it possible for I2C device to have both master and slave functionality?
In multi-master system, sometime an I2C device may need to realize both master and slave functionality.
For example an I2C DEVICE_A needs to write data to EEPROM device and also DEVICE_A needs to send data to an I2C master DSP when requested. In this case as soon as DEVICE_A detects a start condition on bus from DSP it can immediately switch to slave mode and when DEVICE_A detects STOP condition from master it can switch to master mode.
Is it possible to add more than one slave device from same manufacturer to I2C bus? How?
Yes, generally I2C device manufacture divides 7 bit slave address bits in two parts.
- Fixed Bits – These are fixed bit pattern and can’t be changed
- Configurable Bits – These bit combination can be used to differentiate devices from same manufacture. These can be software or hardware configurable.
- Software configurable means, for example general call command can be used to write the configurable bits of slave address.
- Hardware configurable means, slave device writes configurable bits based on digital inputs connected to it.
Below is an example.
What is bit banging in I2C? What is disadvantage of using it?
Bit banging is technique used to realize I2C communication using software instead of using dedicated hardware. Where two GIPO pins of device are configured to behave as SCL and SDA and for any data transfer over bus software is responsible to monitor/set logic levels on this pins as per I2C protocol.
This technique is useful with small device not having dedicated I2C hardware, however most of the time software will be busy monitoring and handling I2C transfer and may have little time to perform other tasks.